1. Field of the Invention
The present invention relates to the field of computer system memory. More specifically, the present invention relates to an apparatus and a method for optimizing control of memory banks populated with standard page mode dynamic random access memory (DRAM) devices and extended data-out (EDO) DRAMs in a memory subsystem.
2. Description of Related Art
An important component of any computer system is a memory array. The memory array is used for storage of data and instructions for the processor and other resources in the computer system. Many prior art computers support a number of memory configurations in the memory subsystem. Some of these memory configurations are implemented by installing memory devices of various types and sizes in the memory banks of the memory subsystem.
In most prior art systems, the memory array comprises dynamic random access memory (DRAM) devices. Most system designers use the DRAM devices in main memory because of their relatively low cost and low power consumption. However, the demanding set-up and hold-times associated with DRAMs frequently prevents computer systems from realizing the greatest performance possible given a chosen microprocessor. For example, Intel""s i486(trademark) microprocessor is capable of performing four consecutive 32-bit reads; however, prior art DRAM main memories could not support such data bursting without complex interface circuitry.
To improve the performance of the DRAM devices, many system designers use page mode DRAMs. In a paged memory device memory is typically accessed by the underlying processor of the computer system by issuing an address that selects a particular location in the memory array. The address is then loaded into a memory controller which handles the task of providing row and column addresses used by the DRAM from the address provided by the processor. The additional hold timing requirement contributes to delays in the delivery of data to the processor.
To alleviate the delays caused in accessing data from the main memory, system designers use a fast performance DRAM device known as the Extended Data Out DRAM (EDO DRAM) which has the same packaging and power characteristics as the page mode DRAMs, but has different timing requirements than the standard page mode DRAMs and does not cause the delays that are characteristic of the standard page mode DRAMS.
The availability of EDO and standard page DRAM devices allow the system designer to design a memory system that can be entirely installed with either the EDO or standard page mode DRAMs. However, the system designer is not able to effectively integrate the EDO and page mode DRAM in the same system without incurring some penalties. For example, if a system designed to handle page mode DRAMs is integrated with EDO DRAMs, the system is not able derive the performance benefits of the EDO DRAMs because of the timing and control restraints imposed by the memory banks in the page mode DRAM system. Mixing the two DRAM types therefore slows performance since the EDO DRAM has to use page mode timings or will not work at all. Similarly, if a system designed to handle EDO DRAMs is integrated with page mode DRAMs, the user is not able to derive the performance advantages expected since the page mode DRAMs are not able to perform as fast as EDO DRAMs due to the differences in timing and control requirements.
Thus, a system that effectively preserves the performance of EDO DRAM banks while ensuring the correct operation of standard page mode DRAMs is needed.
The present invention provides a method and apparatus for optimizing memory banks populated with a standard page mode dynamic random access memory device (DRAM) and an extended data-out (EDO) DRAM in a memory subsystem. The preferred embodiment includes a DRAM controller that supports both EDO DRAMs and page mode DRAMs installed in different memory banks simultaneously in the memory subsystem. The DRAM controller includes a plurality of configuration registers-each a bit wide-having stored information that identifies the type of DRAM device installed in a memory bank. Particularly, each configuration register corresponds to one or more rows of memory banks of DRAMs installed in the memory subsystem.
The DRAM controller further includes a DRAM bank decoder having decoding logic for decoding bank locations responsive to address requests from the processor in the computer system to the memory subsystem. The preferred embodiment further includes a detection logic circuit for detecting bits specified by the configuration registers corresponding to each memory bank populated with a DRAM device. The detection logic uses the weak pull-down times during memory accesses to differentiate memory accesses to a memory bank installed with a standard page mode DRAM or an EDO DRAM. The detection logic in combination with the decode logic determines whether memory bank locations in the memory subsystem is populated or not.
Memory access control signals comprising a row address strobe (RAS), a column address strobe (CAS), and an address strobe (ADS) are utilized by the preferred embodiment for control and timing requirements of the DRAM devices installed in the memory subsystem. A CAS state machine controls the various states of accesses to the DRAM devices. The CAS state machine in combination with the detection logic determines whether an address received by the memory subsystem is designated to the standard page mode DRAM or the EDO DRAM.
Advantages of the DRAM controller of the preferred embodiment include the effective control of various types of DRAM memory devices with different control and timing requirements in the same memory subsystem without degrading performance. The preferred embodiment also has the advantage of automatically storing information for identifying the type of memory device installed in a memory bank to spare the system user the inconvenience of determining the memory type and then manually setting hardware switches to configure memory. The preferred embodiment further has the advantage of preserving the performance of the EDO DRAM banks and the correct operation of the page mode banks at a relatively low hardware cost. The preferred embodiment also allows the re-use of existing page mode DRAMs in new systems designed for EDO DRAMs, without sacrificing the performance of the EDO DRAMs that may already be installed in the new system.
The CAS state machine of the preferred embodiment allows memory access requests to either the standard page mode DRAM or the EDO DRAM without inserting an inordinate amount of wait states to slow the system down.
The features and advantages described in the specification are not all inclusive, and particularly, many additional features and advantages will be apparent to one of ordinary skill in the art in view of the drawings, specification and claims hereof. Moreover, it should be noted that the language used in the specification has been principally selected for readability and instructional purpose, and therefore resort to the claims is necessary to determine the inventive subject matter.